Scan testing has been the foundation of digital-device production test for many years. Several innovations have been developed to keep up with the growth in pattern-set sizes brought about by large ...

Automatic test-pattern generation (ATPG) has played a key role in semiconductor logic test, but several trends driving the need for semiconductor test quality are challenging traditional ATPG tools.

In the 1990s, Carnegie Mellon researchers created a comprehensive scan-test cost model that demonstrated how design for test (DFT) contributes to profitability (Ref. 1). With scan compression in wide ...

There is a rapidly growing interest in the use of structural techniques for testing random logic. In particular, much has been published on new techniques for on-chip compression of automatic test ...

MOUNTAIN VIEW, Calif. -- Oct. 5, 2015 -- Synopsys, Inc. (Nasdaq: SNPS) today announced a new, breakthrough ATPG and diagnostics technology that delivers 10X faster run time and 25 percent fewer test ...

For testing complex chip designs it makes sense to combine the two most common test methodologies -logic built-in self-test (LBIST) and automatic test pattern generation (ATPG), writes Amer ...

Low-power design and fast testing at the fab are not happy bedfellows. As Giri Podichetty of Mentor Graphics explains at Semiwiki and in a white paper, “the goal of automatic test pattern generation ...

Patterns created using advanced fault models provide higher test coverage, improved defect detection, and higher-yielding ...

Recent and continuing trends in the semiconductor industry pose challenges to IC test-data volumes, test application times, and test costs. The industry has thus far succeeded in containing test costs ...

As semiconductor applications in automotive, data center, and high-performance computing grow increasingly mission-critical, the industry faces mounting pressure to achieve near-perfect manufacturing ...